FIG. 5 is a cross-sectional view of a conventional field effect transistor made of compound semiconductor materials. The cross-sectional view of FIG. 5 shows one transistor and part of another transistor that are part of a larger group of interconnected transistors formed on a common substrate.
The transistor includes a semi-insulating substrate 1, for example, gallium arsenide, on which are successively disposed a buffer layer 2 and an active layer 3. Layers 2 and 3 are of opposite conductivity types and generally the active layer 3 is n-type. A source electrode 4, a gate electrode 5, and a drain electrode 6 are disposed on the active layer 3. The amount of current flowing between the source and drain electrodes through the active layer 3 is controlled by the signal applied to the gate electrode 5 which generally forms a Schottky barrier with the active layer 3.
The substrate 1 is disposed on a plated heat sink (PHS) 7 which is grounded in most circuitry including the illustrated structure. Likewise, the source electrode 4 is usually grounded. The ground connection from the source electrode 4 to the PHS 7 is made through a via hole structure 8. The via hole structure 8 includes a hole penetrating through the active layer 3, the buffer layer 2, and the substrate 1 to the PHS 7, the hole being defined by a side wall 9 of those layers and the substrate, and an electrically conducting material 10, such as gold, disposed within the via hole contacting the side wall 9, the PHS 7, and the source electrode 4. The electrically conducting material 10 electrically connects the source electrode 4 to the PHS 7. The via hole structure 8 provides a relatively low inductance ground connection for the source electrode 4. The drain electrode 6 is connected through a metallization 11 to another part of the circuit. The electrically conducting material 10 also connects the source electrode 4 to another source electrode 4 of an adjacent transistor.
In the conventional device, the via hole structure 8 is formed after the buffer layer 2 and active layer 3 are grown on the substrate 1. Using conventional photolithographic techniques, before or after the PHS 7 is formed, the via hole is etched through the substrate and the buffer and active layers. After the deposition of the source electrode 4 and etching of the via hole, the electrically conducting material 10 is deposited in the via hole and in contact with the source electrode 4 using conventional techniques, such as vapor deposition and lift-off.
In the conventional field effect transistor of FIG. 5, both the buffer layer 2 and the active layer 3 are directly in contact with the electrically conducting material 10 of the via hole structure 8. A pn junction is formed between the active layer 3 and the buffer layer 2. Generally, current flowing in the active layer 3 between the source and drain electrodes is discouraged from flowing into or out of the buffer layer 2 by at least one of the pn junctions lying below the source electrode 4 and the drain electrode 6. Ordinarily, at least one of those junctions is reverse biased. However, the adjacent electrically conducting material 10 of the via hole structure 8 can short-circuit the reverse biased junction that lies below the source electrode 4. Therefore, under certain biasing conditions, an undesirable leakage current can flow between the drain electrode 6 and the source electrode 4 through the active layer 3, the buffer layer 2, and the electrically conducting material 10.